PIC18C452T-E/L【PDF 65/279 页】IC MCU OTP 16KX16 A/D 44PLCC

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3889

61页 62页 63页 64页 [65页]66页 67页 68页 69页

172

8197C–AVR–05/11

ATtiny261A/461A/861A

After RESET is set low, the Programming Enable instruction needs to be executed first before

program/erase operations can be executed.

Note:

In Table 18-9, above, the pin mapping for SPI programming is listed. Not all parts use the SPI pins

dedicated for the internal SPI interface.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High:> 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

18.6.1

Serial Programming Algorithm

When writing serial data to the device, the data is clocked on the rising edge of SCK. When

reading, data is clocked on the falling edge of SCK. See Figure 19-3 and Figure 19-4 for timing

details.

To program and verify the device in Serial Programming mode, the following sequence is recom-

mended (see four byte instruction formats in Table 18-11):

Power-up sequence: Apply power between V

CC and GND while RESET and SCK are

set to “0”.

– In some systems, the programmer can not guarantee that SCK is held low during

power-up. In this case, RESET must be given a positive pulse after SCK has been

set to '0'. The duration of the pulse must be at least t

RST (the minimum pulse width on

RESET pin, see Table 19-4 on page 188) plus two CPU clock cycles.

Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

The serial programming instructions will not work if the communication is out of syn-

chronization. When in sync. the second byte (0x53), will echo back when issuing the

third byte of the Programming Enable instruction. Whether the echo is correct or not, all

four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give

RESET a positive pulse and issue a new Programming Enable command.

The Flash is programmed one page at a time. The memory page is loaded one byte at

a time by supplying the 5 LSB of the address and data together with the Load Program

memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program memory

Page is stored by loading the Write Program memory Page instruction with the 6 MSB

of the address. If polling (RDY/BSY) is not used, the user must wait at least t

WD_FLASH

Table 18-9.

Pin Mapping Serial Programming

Symbol

Pins

I/O

Description

MOSI

PB0

Serial Data in

MISO

PB1

Serial Data out

SCK

PB2

Serial Clock

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式